Conventional continuous time ΔΣ ADCs typically include an analog filter response to an analog input signal and a low resolution clocked quantizer which provides a digital output. The output from the quantizer is input to digital-to-analog converters (DACs). The quantized signal from the DACs is fed back to the loop filter. The quantizer is typically clocked at a rate much higher than the bandwidth of the signal input to the loop filter. Conventional quantizers may include a Flash or SAR ADC. Because the quantizer is often clocked at a higher rate than the ADCs signal bandwidth, the quantizer consumes, depending on its resolution, a significant amount of power.
One solution to mitigate the power problem associated with using a conventional quantizer is to replace it with a VCO based quantizer, which leverages the phase of the VCO. However, using a VCO based quantizer instead of a conventional quantizer may result in bit shifting in the digital output. The bit shifting can affect the performance and accuracy of the DACs.
A typical conventional VCO phase quantizer includes a multi-stage VCO connected to a multi-stage phase quantizer. The multi-stage phase quantizer determines the phase of the VCO by comparing the phase of a VCO for a particular sample to a reference phase and generates a quantized phase difference value. However, a conventional VCO quantizer may also produce an output with shifted bits that can affect the performance and accuracy of the DACs.
Thus, there is a need for ΔΣ ADC which can mitigate bit shifting of a multi-stage phase quantizer.